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Central processing unit
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241	The finite state automaton based pipeline hazard recognizer and instruction scheduler in GCC Vladimir N. Makarov Red Hat Add to Reading List Source URL: gcc.cybermirror.org Language: English - Date: 2004-08-29 18:00:00 Central processing unit Classes of computers Parallel computing Models of computation Hazard Superscalar Instruction set Register renaming Reduced instruction set computing Computer architecture Computing Computer engineering
242	do i: Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2009-05-20 10:28:00 Central processing unit Parallel computing Chunk Process CPU cache Computer architecture Computing Computer hardware Computer memory
243	Main Memory Performance for Database Systems Kenneth A. Ross Columbia University 1 Add to Reading List Source URL: hpts.ws Language: English - Date: 2012-04-19 12:03:23 Cache Central processing unit Computer architecture Classes of computers CPU cache SIMD Memory hierarchy In-memory database Processor register Computing Computer hardware Computer memory
244	HDTrans: An Open Source, Low-Level Dynamic Instrumentation System Swaroop Sridhar Jonathan S. Shapiro Eric Northup Prashanth P. Bungale Add to Reading List Source URL: srl.cs.jhu.edu Language: English - Date: 2007-09-20 09:41:43 Compiler optimizations Software optimization Central processing unit Profilers Binary translation CPU cache Pin Profiling Fortran Computing Computer programming Software engineering
245	G522REV. 1.1 ™ Add to Reading List Source URL: www-01.ibm.com Language: English - Date: 2015-06-05 16:01:21 Central processing unit Computer memory Virtual memory Instruction set architectures Power Architecture CPU cache Translation lookaside buffer PowerPC Memory management unit Computer architecture Computer hardware Computing
246	MASSACHUSETTS INSTITUTE OF TECHNOLOGY DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCEComputation Structures Spring 2006 Quiz #5: May 12, 2006 Name Add to Reading List Source URL: 6004.csail.mit.edu Language: English - Date: 2012-01-17 10:22:28 Semaphore Concurrency control Lock Central processing unit
247	Secure Microcontroller AT90SC20818RCV Summary Features General Add to Reading List Source URL: www.insidesecure.com Language: English Central processing unit Computing Computer memory Non-volatile memory EEPROM Memory-mapped I/O Instruction set PIC16x84 Atmel AVR Computer hardware Microcontrollers Computer architecture
248	Maximizing the power of the Cell Broadband Engine processor: 25 ti... http://www-128.ibm.com/developerworks/power/library/pa-celltips1/ Maximizing the power of the Cell Broadband Engine processor: 25 tips to optimal app Add to Reading List Source URL: moss.csc.ncsu.edu Language: English - Date: 2007-02-19 16:22:58 Central processing unit Cell Digital signal processing Classes of computers Computer memory SIMD Data structure alignment CPU cache Instruction set Computing Computer architecture Computer hardware
249	Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • Add to Reading List Source URL: www.atmel.com Language: English - Date: 2015-03-23 20:09:58 Computer engineering Instruction set architectures Central processing unit Interrupt Instruction set Addressing mode Memory-mapped I/O Atmel AVR PIC microcontroller Computer architecture Computer hardware Microcontrollers
250	An Enhanced Implementation of the Allocation Macros in LATEX 2ε, LATEX 2.09, and plain-TEX Bernd Raichle Stettener Str. 73 DEsslingen, FRG Email: Add to Reading List Source URL: mirror.unl.edu Language: English - Date: 2005-06-11 07:32:00 Central processing unit Macro programming languages Register allocation Macro Dc Processor register Constant LaTeX TeX Computing Computer programming Software engineering

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